8048 movp instruction. Ask Question -1. $ begingroup $ Please add a link to the device's datasheet where you found this information. $ endgroup $ – jippie Dec 2 '14 at 6:49. And a 16-bit data pointer. But the 8048 only has 8-bit registers, so it has to do some extra work to determine the full address in program memory. Possible to develop programs quickly for the new microprocessors, and had introduced Intel’s first in-circuit emulator, ICE-80. I had also done some work on Intel's groundbreaking high-level language PLM for the 8-bit processors. And at the time that the 8048 was coming to fruition we divided development. 8048AH datasheet, 8048AH circuit, 8048AH data sheet: INTEL - HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER,alldatasheet, datasheet, Datasheet search site for Electronic Components and Semiconductors, integrated circuits, diodes, triacs, and other semiconductors. 8048P Datasheet, 8048P PDF, 8048P Data sheet, 8048P manual, 8048P pdf, 8048P, datenblatt, Electronics 8048P, alldatasheet, free, datasheet, Datasheets, data sheet. MCS-48 and UPI-41 8048 - 8049 8041 - 8042 Ceibo In-Circuit Emulator Supporting MCS-48 and UPI-41: DS-48. Intel Created Date: 3/21/1999 2:00:07 PM.
Description This oral history panel includes members of the engineering team that developed the 8048 (MCS-48), Intel's first dedicated microcontroller (MCU) chip and the 8748 the first MCU with on-board EPROM.
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Sign up| EESchema-DOCLIB Version 2.0 |
| # |
| $CMP 16450 |
| D PC16450, Universal Asynchronous Receiver/Transmitter, PDIP-40 |
| K 1ch UART |
| $ENDCMP |
| # |
| $CMP 16550 |
| D PC16550D, Universal Asynchronous Receiver/Transmitter with FIFOs, PDIP-40 |
| K 1ch UART FIFO |
| F http://www.ti.com/lit/ds/symlink/pc16550d.pdf |
| $ENDCMP |
| # |
| $CMP 8035 |
| D MCS-48 8-bit Microcontroller, No (EP)ROM, 64B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8039 |
| D MCS-48 8-bit Microcontroller, No (EP)ROM, 128B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8040 |
| D MCS-48 8-bit Microcontroller, No (EP)ROM, 256B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8048 |
| D MCS-48 8-bit Microcontroller, 1KB Mask ROM, 64B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8049 |
| D MCS-48 8-bit Microcontroller, 2KB Mask ROM, 128B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8050 |
| D MCS-48 8-bit Microcontroller, 4KB Mask ROM, 256B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8086_Max_Mode |
| D 8086 (maximum mode), 16-Bit HMOS Microprocessor, PDIP-40 |
| K MPRO |
| F http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086/231455-006.pdf |
| $ENDCMP |
| # |
| $CMP 8086_Min_Mode |
| D 8086 (minimum mode), 16-Bit HMOS Microprocessor, PDIP-40 |
| K MPRO |
| F http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086/231455-006.pdf |
| $ENDCMP |
| # |
| $CMP 8087 |
| D Math Coprocessor for Intel 8086/8088/80186/80188 microprocessors, PDIP-40 |
| K FPU |
| F http://datasheets.chipdb.org/Intel/x86/808x/datashts/8087/205835-007.pdf |
| $ENDCMP |
| # |
| $CMP 8088 |
| D 8088 (minimum mode), 8-Bit HMOS Microprocessor, PDIP-40 |
| K MPRO |
| F http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf |
| $ENDCMP |
| # |
| $CMP 8088_Max_Mode |
| D 8088 (maximum mode), 8-Bit HMOS Microprocessor, PDIP-40 |
| K MPRO |
| F http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf |
| $ENDCMP |
| # |
| $CMP 8088_Min_Mode |
| D 8088 (minimum mode), 8-Bit HMOS Microprocessor, PDIP-40 |
| K MPRO |
| F http://datasheets.chipdb.org/Intel/x86/808x/datashts/8088/231456-006.pdf |
| $ENDCMP |
| # |
| $CMP 8237 |
| D Programmable DMA Controller, PDIP-40 |
| K 8237 DMA |
| F https://pdos.csail.mit.edu/6.828/2012/readings/hardware/8237A.pdf |
| $ENDCMP |
| # |
| $CMP 8250 |
| D PC8250A, Universal Asynchronous Receiver/Transmitter, PDIP-40 |
| K 1ch UART |
| $ENDCMP |
| # |
| $CMP 8252 |
| D Universal Asynchronous Receiver/Transmitter, PDIP-28 |
| K UART Serial Interface |
| $ENDCMP |
| # |
| $CMP 8253 |
| D Programmable Interval Timer, PDIP-24 |
| K Timer Counter |
| F http://www.cpcwiki.eu/imgs/e/e3/8253.pdf |
| $ENDCMP |
| # |
| $CMP 8254 |
| D Programmable Interval Timer, PDIP-24 |
| K Timer Counter |
| F http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf |
| $ENDCMP |
| # |
| $CMP 8255 |
| D Programmable Peripheral Interface, PDIP-40 |
| K 8255 PPI |
| F http://aturing.umcs.maine.edu/~meadow/courses/cos335/Intel8255A.pdf |
| $ENDCMP |
| # |
| $CMP 8255A |
| D Programmable Peripheral Interface, PDIP-40 |
| K 8255 PPI |
| F http://aturing.umcs.maine.edu/~meadow/courses/cos335/Intel8255A.pdf |
| $ENDCMP |
| # |
| $CMP 8259 |
| D 8259, Programmable Interrupt Controller, PDIP-28 |
| K PIC |
| F http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf |
| $ENDCMP |
| # |
| $CMP 82720 |
| D Graphics Display Controller, PDIP-40 |
| K Graphics Controller |
| $ENDCMP |
| # |
| $CMP 8284 |
| D Clock Generator and Driver for i8086/88 Microcontrollers, PDIP-18 |
| K Clock Generator |
| F http://www.cpu-galaxy.at/cpu/ram%20rom%20eprom/other_intel_chips/other_intel-Dateien/D8284A_Datasheet.pdf |
| $ENDCMP |
| # |
| $CMP 8288 |
| D Bus Controller for Intel 8086/8088/80186/80188 microprocessors, DIP-20 |
| K Bus Controller |
| F http://www.datasheets360.com/pdf/7208679415653955300 |
| $ENDCMP |
| # |
| $CMP 82C54 |
| D CHMOS Programmable Interval Timer, PDIP-24 |
| K Timer Counter |
| F http://download.intel.com/design/archives/periphrl/docs/23124406.pdf |
| $ENDCMP |
| # |
| $CMP 82C54_PLCC |
| D CHMOS Programmable Interval Timer, PLCC-28 |
| K Timer Counter |
| F http://download.intel.com/design/archives/periphrl/docs/23124406.pdf |
| $ENDCMP |
| # |
| $CMP 82C55A |
| D CHMOS Programmable Peripheral Interface, PDIP-40 |
| K 8255 PPI |
| F http://jap.hu/electronic/8255.pdf |
| $ENDCMP |
| # |
| $CMP 82C55A_PLCC |
| D CHMOS Programmable Peripheral Interface, PLCC-44 |
| K 8255 PPI |
| F http://jap.hu/electronic/8255.pdf |
| $ENDCMP |
| # |
| $CMP 8748 |
| D i8748, MCS-48 8-bit Microcontroller with Internal EPROM, 1KB EPROM, 64B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP 8749 |
| D i8748, MCS-48 8-bit Microcontroller with Internal EPROM, 2KB EPROM, 128B RAM, DIP-40 |
| K MCS-48 uC Microcontroller |
| $ENDCMP |
| # |
| $CMP I386EX_PQFP |
| D Intel I386EX Embedded microprocessor, PQFP-132 |
| K MPRO |
| $ENDCMP |
| # |
| #End Doc Library |
| WikiProject Computing | ||||||||
| ||||||||
Interview with 8048 designers. Is the link worthwhile enough to be included in the 8048 page? http://www.computerhistory.org/collections/accession/102658328 I leave the decision to wikipedia maintainers (this note added 2010-01-16)http://archive.computerhistory.org/resources/text/Oral_History/Intel_8048/102658328.05.01.pdf
Was it really _the_first_ microcontroller? Are the ROM and RAM both on-chip?--Anonymous
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Table added --JWBE (talk) 16:31, 4 September 2010 (UTC)
Yes, there is one with EPROM. I took a picture of one a put it on the page. - Bryce
The hunt for the PROM version revealed information about other derivatives. The updated table contains additional UPIs. -- Arnim

Table added --JWBE (talk) 16:31, 4 September 2010 (UTC)

This seems like very odd language - an EPROM that can actually only be programmed once screams 'PROM' to me. Unless we're getting our acronyms mixed up, it's electronically programmable, and someone's therefore knocked out the second E ('erasable') of EEPROM rather than the first?
Given the discussion above, does anyone mind if I'm 'bold' and just change that? If the Intel spec sheets actually do say 'OTP EPROM' then feel free to revert it.. 91.125.59.216 (talk) 11:05, 16 March 2014 (UTC)
Contribution: gezzus.thx@gmail.com
OTP = One Time programable's are a form of mask programmable rom that are written one time and cannot be written again.
OTP's use byte width fusible links (8 fuse links per byte per memory location) which are blown 'open to create logic '0' and unblown to maintain a logic '1', these are known More commonly as PROMS and were the earliest form of permanent code/data storage for micro controllers & microprocessors until UV erased memory devices called eproms came along in the mid 1970's and remained the standard for programmable devices up till the early 1990's.
At which time a newer memory device type called EEPROM that used electrical current to both program and erase a memory device instead of UV light. these devices gave birth to what we see today Serial EEPROM & Serial Flash memories etc — Preceding unsigned comment added by 24.36.18.57 (talk) 08:10, 25 February 2015 (UTC)
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MIPS usually refers to performance relative to a VAX 11/780 not literal instructions, and most instructions don't execute in one cycle anyway. 24.93.185.231 (talk) 01:43, 23 May 2017 (UTC)